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Split ARM64 prefetches at the cache line size #9599
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alexreinking
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alexreinking/simplify-div-bounded-offset
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alexreinking/arm-prefetch-line-size
Oct 26, 2026
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Out of curiosity, have you tried 256 instead of 128?
Context: not long ago I wrote a benchmark, and found out that even though the cache line size of Apple Silicon is 128 bytes long, for false-sharing scenarios, using 256 bytes gave better performance still.
Curious to see if it would have an effect here.