[alexreinking]

reduce_prefetch_dimension splits every ARM prefetch into 32-byte pieces, which is the smallest cache line size of 32-bit ARM cores. 64-bit ARM cores have lines of at least 64 bytes, and Apple's cores have 128-byte lines. On Apple silicon, 3 of every 4 prfm instructions therefore request a line that was already requested.

This PR splits prefetches at:

• 128 bytes for 64-bit ARM on macOS and iOS;
• 64 bytes for other 64-bit ARM targets;
• 32 bytes for 32-bit ARM, as before.

correctness_prefetch used to check only the host target. It now also lowers its tests for x86-64-linux, arm-32-linux, arm-64-linux, arm-64-macos, and arm-64-ios.

Benchmarks

The benchmark is an int8 smmla gemm from the GGML app (#9511), with a Func::prefetch of the weight stream added at offsets 2, 4, and 8 iterations of the K loop. Each region is 128 bytes per iteration. Times are on an M3 Max, relative to the same kernel without the prefetch (lower is better), min of 3 runs:

K×N×M, threads	32 B (before)	128 B (this PR)
4096×4096×32, T1	1.055–1.057	0.994–0.998
4096×14336×32, T1	1.056–1.085	1.011–1.028
14336×4096×32, T1	1.043–1.087	1.002–1.031
4096×14336×128, T1	1.023–1.031	0.979–0.984
4096×4096×32, T10	1.043–1.059	0.994–1.003
4096×14336×32, T10	1.053–1.059	0.995–1.007

With the old split, the extra prefetch instructions made the kernel 3–9% slower. With this PR they cost nothing measurable. (The hardware prefetchers already cover this kernel's weight stream, so prefetching doesn't make it faster either.)

Stacked on #9520.

Checklist

• Tests added or updated (not required for docs, CI config, or typo fixes)
• Documentation updated (if public API changed)
• Python bindings updated (if public API changed)
• Benchmarks are included here if the change is intended to affect performance.
• Commits include AI attribution where applicable (see Code of Conduct)

Validation: correctness_prefetch and correctness_bad_prefetch pass; the full ctest -L correctness run at the top of the stack passed 703/704 (the only failure is correctness_cross_compilation, because the local LLVM has no Hexagon backend).

[slomp]

LGTM, with an experiment you can try.

[slomp]

Out of curiosity, have you tried 256 instead of 128?

Context: not long ago I wrote a benchmark, and found out that even though the cache line size of Apple Silicon is 128 bytes long, for false-sharing scenarios, using 256 bytes gave better performance still.

Curious to see if it would have an effect here.

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 73.05%. Comparing base (9638399) to head (bc53255).

Additional details and impacted files

@@                             Coverage Diff                              @@
##           alexreinking/simplify-div-bounded-offset    #9599      +/-   ##
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+ Coverage                                     73.02%   73.05%   +0.03%     
============================================================================
  Files                                           263      263              
  Lines                                         82415    82422       +7     
  Branches                                      20156    20159       +3     
============================================================================
+ Hits                                          60181    60213      +32     
- Misses                                        15913    15919       +6     
+ Partials                                       6321     6290      -31     

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