This roadmap helps beginners who want to start a career in FPGA and ASIC (chip) design, and helps current practitioners broaden their skills. FPGA and ASIC engineers write the same kind of code (RTL) and share most of the fundamentals; the main differences are in the tools, the implementation flow and the cost of a mistake.
Tip
To differentiate between the types of learning resources and the quality of their content, specific symbols are used before each item.
Resource types:
- 📘 : Books
- 🎞️ : Videos
- 📝 : Write-ups, articles, and blog posts
- 🔗 : Other links that do not fit into any of the above categories
Content quality symbols:
- 👶 : Easy-to-understand and beginner-friendly resources. Refer to them if you do not have prior knowledge in a topic.
- 💎 : Well-known references that have truly invaluable and comprehensive content. Refer to them if you want to deepen your understanding of a topic.
Topic priority (shown under each topic in the Roadmap):
- Required : Every engineer in the field needs it.
- Recommended : Needed for most jobs or for a given specialization.
- Optional : Useful in specific domains or for going deeper.
New to the field? Start with the suggested learning path below, and keep this in mind while you study:
Warning
You do not need to read every book and article or watch every video listed here. Study enough to understand a topic, then practice by writing and simulating real designs. Hardware design is learned by doing.
- Learn digital logic and computer architecture. Gates, flip-flops, finite-state machines, and how a simple CPU works: Nand2Tetris, Computation Structures, and the book Digital Design and Computer Architecture (see Digital Logic and Computer Architecture).
- Pick one HDL and practice small problems. Verilog/SystemVerilog with HDLBits, or VHDL with VHDLwhiz. Do not worry about the "best" language: the concepts transfer (see Hardware Description Languages).
- Set up free simulation tools. Icarus Verilog or Verilator (or GHDL for VHDL) with GTKWave, or simply use EDA Playground in the browser (see Simulation, Testbenches and Debugging).
- Write clean, synthesizable RTL. Learn state machines, registers, resets and coding style before writing big designs (see RTL Design Practices).
- Run the full FPGA flow on real hardware. Synthesize, place-and-route and program a cheap board (see Getting an FPGA Board) with Nandland or Project F.
- Learn timing, clock domain crossing and standard interfaces. These separate hobby designs from professional ones (see Timing Analysis and Constraints, Clock Domain Crossing and Resets, and Interfaces, Protocols and Memory).
- Build projects. A UART, a VGA/HDMI display controller, a small RISC-V CPU (see Projects).
- Specialize. Go deeper into implementation, verification or ASIC design.
A general collection of courses, tutorials, books and websites to get started. Resources for specific topics are listed in the Roadmap section below, and neighboring fields (electronics, RF, power electronics) are at the end of this section.
- 📝👶 What are FPGAs?
- 🎞️👶 Introduction to FPGA - Shawn Hymel (YouTube Playlist)
- 🔗👶 FPGA 101 - Nandland
- 🎞️ Nandland (YouTube Channel)
- 🎞️👶 FPGAs for Beginners (YouTube Channel)
- 📘👶 Getting Started with FPGAs - Russell Merrick (Nandland)
- 📘👶 Free Range VHDL - Bryan Mealy, Fabrizio Tappero
- 🔗👶 Nand2Tetris - Build a Modern Computer from First Principles
- 🎞️👶 Coursera - Digital Systems: From Logic Gates to Processors
- 🔗 MIT 6.111 - Introductory Digital Systems Laboratory
- 🎞️💎 Digital Design and Computer Architecture - Onur Mutlu, ETH Zürich (YouTube Channel)
- 🔗💎 Zero to ASIC Course
- 🎞️ Coursera - VLSI CAD Part I: Logic
- 🔗 asic-world.com
- 🔗 Learn Chip Design & Verification
- 📝👶 Verilog Tutorial - ASIC World
- 📝👶 Verilog Tutorial - ChipVerify
- 🔗 Verification Academy
- 📝 VHDL vs Verilog vs SystemVerilog: Which Hardware Language Should You Learn First for a Successful Career?
- 🔗 Digital Electronics Deeds
- 📝👶💎 Project F - FPGA Tutorials
- 🔗💎 Tiny Tapeout: from idea to chip design in minutes!
- 📝💎 Learning FPGA, yosys, nextpnr, and RISC-V
- 🔗💎 Doulos - Global Independent Leaders in Design and Verification KnowHow
- 🎞️ Coursera - FPGA Design for Embedded Systems Specialization
- 🎞️ Coursera - Computer Architecture
- 🎞️ Coursera - Hardware Security
- 🎞️ Udemy – FPGA Embedded Design, Part 1 - Verilog
- 🎞️ Udemy – FPGA Embedded Design, Part 2 - Basic FPGA Training
- 🎞️ Udemy – FPGA Embedded Design, Part 3 - EDA Tools
- 🎞️ Udemy – FPGA Embedded Design, Part 4 - Microprocessor Design
- 🔗👶 FPGA 4 Students
- 🔗👶 Access an FPGA right now!
- 📝 Designing a Custom AXI Slave (Avnet PDF)
- 🔗💎 Computation Structures
- 🎞️ YouTube Playlist - CMOS Digital VLSI Design
- 🎞️ YouTube Playlist - Basic Computer Architecture
- 🎞️ YouTube Playlist - Hardware Modeling using Verilog
- 🎞️ YouTube Playlist - Microprocessors and Microcontrollers
- 🔗 MakerCode
- 🔗 Logi-Code
- 🔗 Sistenix
Electronics, semiconductor physics, RF, power electronics and microcontrollers are not required to start with FPGA/ASIC design, but they help for board-level work, analog/mixed-signal design and chip fabrication.
- 🎞️👶 Neso Academy - Electronics & Communication
- 🎞️ edX - MITx: Circuits and Electronics 1: Basic Circuit Analysis
- 🎞️ Coursera - Introduction to Electronics
- 🎞️ Coursera - Semiconductor Physics
- 🎞️ Coursera - MOSFET
- 🎞️ Coursera - Introduction to Microfabrication
- 🎞️ Coursera - Power Electronics Specialization
- 🎞️ Coursera - RF MM-Wave Circuit Design
- 🎞️ Coursera - RF/Microwave Design - S-Parameter Analysis
- 🎞️ Coursera - RF/Microwave Design - Impedance Matching
- 🎞️ Coursera - RF/Microwave Design - Antenna Design
- 🎞️ Coursera - Microwave Antenna
- 🎞️ Coursera - ARM Cortex STM32 Deep Dive: Mastering Embedded Systems
Project ideas and complete open-source designs to practice on and read. Start small (blinking LEDs, a UART, a display controller) before moving on to CPUs and SoCs.
- 🔗 FPGA 4 Fun
- 🔗 AMD Based FPGA Projects - Whitney Knitter
- 🔗 AMD Based FPGA Projects - Adam Taylor
- 🔗 Aegis - MidstallSoftware
- 🔗 OpenSignal
- 📝 Quake 2 on FPGA
- 🔗 mVIDIA
- 🎞️ RISC-V Single Cycle Core in Verilog
- 🎞️ SPI Project in FPGA - Ambient Light Sensor
- 🔗 FPGA Conway
- 🔗 Verilaxi
- 🔗 OpenTitan - open-source silicon root of trust (lowRISC)
- 🔗 PULP Platform - open-source RISC-V hardware
- 📝 ZipCPU Blog - FPGA, formal verification and CPU design
- 🔗 VexRiscv - FPGA-friendly RISC-V CPU
- 🔗 PicoRV32 - Size-optimized RISC-V CPU
- 🔗 Verilog Ethernet - Ethernet MAC, UDP/IP and PCIe designs (Alex Forencich)
You can learn a lot with simulation alone, but programming a real board makes the concepts concrete. Pick a board whose toolchain you are comfortable with:
- 🔗👶 Digilent Basys 3 (AMD Artix-7) - Classic teaching board used by many university courses; uses the free AMD Vivado.
- 🔗👶 iCEBreaker (Lattice iCE40) - Fully supported by the open-source Yosys + nextpnr toolchain.
- 🔗👶 Sipeed Tang Nano 9K (Gowin) - Very cheap board with HDMI output, supported by open-source tools.
- 🔗 Alchitry Boards - Beginner-oriented boards with their own tutorials.
- 🔗👶 Access an FPGA right now! - No board? Use a remote one.
The world of FPGA and ASIC engineering thrives on two crucial disciplines: Implementation Engineering and Verification Engineering. While intertwined, each plays a distinct role in bringing innovative ideas to life in programmable hardware or custom silicon. Engineers who target custom chips additionally need ASIC-specific physical design and sign-off skills.
Implementation Engineers are the architects of the design, meticulously crafting it by translating algorithms and functionalities into hardware configurations. They leverage their expertise in hardware description languages and synthesis tools to optimize design performance and resource utilization.
Verification Engineers, on the other hand, safeguard the design's integrity. They design and execute comprehensive test strategies, utilizing advanced simulation tools and real-world test setups. By comparing expected behavior with actual outputs, they identify and eliminate errors, ensuring the final product functions as intended.
Both disciplines are equally critical, working hand-in-hand throughout the development process. Implementation engineers rely on verification feedback to refine their designs, while verification engineers depend on accurate implementation models to create effective tests.
The topics are ordered roughly in the sequence in which you should learn them: Common Skills first (needed by everyone), then the Implementation, Verification and ASIC Design specializations, and finally domains, community and career. Each topic is tagged with its priority.
Priority: Required
Logic gates, combinational and sequential circuits, finite-state machines, memory architectures, and how CPUs and memory systems work. This can be extended to specialized architectures, such as Graphics Processing Units (GPUs) or custom accelerator designs.
- 🔗👶 Nand2Tetris - Build a Modern Computer from First Principles
- 🔗💎 Computation Structures (MIT 6.004)
- 📘💎 Digital Design - Morris Mano, Michael Ciletti
- 📘👶💎 Digital Design and Computer Architecture: ARM Edition - Sarah Harris, David Harris
- 📘👶💎 Digital Design and Computer Architecture: RISC-V Edition - Sarah Harris, David Harris
- 🔗 Digital Design and Computer Architecture - Book Companion Site (slides, labs, errata)
- 🎞️💎 Digital Design and Computer Architecture - Onur Mutlu, ETH Zürich (YouTube Channel)
- 📘💎 Computer Organization and Design: ARM Edition - David A. Patterson, John L. Hennessy
- 📘👶 Digital Fundamentals - Thomas L. Floyd
- 📝 Tiny Tapeout > Digital Design Guide
- 📝 FPGA Fundamentals - Nandland
- 🎞️👶 Build an 8-bit computer from scratch
- 🔗 The RISC-V Instruction Set Specifications
- 📝 Every GPU Architecture in a Staggering Visual Timeline
- 🔗 IC Design Tips
Priority: Required
FPGA and ASIC tools run mostly on Linux and are driven by scripts. Comfort with the command line, Git, and a scripting language (Tcl, Python, Make, shell) lets you automate builds, simulations and regressions, and is expected in every job.
- 🔗👶💎 The Missing Semester of Your CS Education (MIT)
- 🎞️ Git Tutorial for Beginners: Learn Git in 1 Hour
- 🎞️ Git for Professionals Tutorial - Tools & Concepts for Mastering Version Control with Git
- 📘👶💎 Pro Git - Scott Chacon, Ben Straub
- 🔗 Apache® Subversion®
- 📝 Why you need to learn Tcl
- 📝 Top 10 Tips for efficient Perl Scripting for Chip Designers
- 🔗 Edalize - Python library for driving FPGA and simulator tools
- 🔗 FuseSoC - Package manager and build abstraction tool for FPGA/ASIC IP cores
- 🔗 HDL Containers - Ready-to-use container images of open-source EDA tools (for CI)
Priority: Required
Knowledge of VHDL and/or Verilog is crucial as they're commonly used to design and describe digital circuits. Pick one first and learn the other later; the concepts transfer.
- 📝 VHDLwhiz - Basic VHDL Tutorials
- 🎞️ VHDLwhiz.com (YouTube Channel)
- 📝👶💎 HDLBits — Verilog Practice
- 📝 FPGA designs with Verilog
- 📝👶 Learn Verilog - Nandland
- 📝👶 Learn VHDL - Nandland
- 📘👶 Free Range VHDL - Bryan Mealy, Fabrizio Tappero
- 📝 SystemVerilog Tutorial - ChipVerify
- 🔗 Doulos - SystemVerilog Knowhow
Modern HDLs and HDL-embedded generators (optional, learn them after you are comfortable with Verilog or VHDL):
- 🔗 Veryl
- 📝 Chisel - Hardware construction language embedded in Scala
- 📝 SpinalHDL - Scala-based HDL
- 📝 Amaranth HDL - Python-based HDL
- 🔗 LiteX - Build your own FPGA-based SoC in Python
Priority: Required
Writing code that synthesizes into the hardware you intend: registers versus latches, blocking versus non-blocking assignments, finite-state machine (FSM) coding styles, pipelining, and number representation and arithmetic (fixed-point, multipliers, CORDIC). Bad habits here cause bugs that are hard to find later.
- 📝👶 Verilog Blocking and Non-Blocking Statements - ChipVerify
- 📝💎 Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! - Clifford E. Cummings
- 📝👶 Verilog Finite State Machine - ChipVerify
- 📝 Verilog Coding Style Guide - lowRISC
- 📝👶 Fixed Point Numbers in Verilog - Project F
- 📝 CORDIC - ZipCPU
- 📝 Strategies for Pipelining - ZipCPU
Pipeline design and flow control (skid buffers, FIFOs): decoupling stages, managing backpressure, and avoiding timing bottlenecks in pipelined designs.
- 📝 Skid Buffer (ZipCPU)
- 📝 Pipeline Skid Buffer (FPGA CPU)
- 📝 Designing Skid Buffers for Pipelines (Chipmunk Logic)
- 📝 A Case Study on Effective Pipeline Design in Digital System
Priority: Required
Every designer simulates their own code. Learn to write simple self-checking testbenches, read waveforms, lint your code, and debug on real hardware with logic analyzers built into the FPGA. (Advanced verification methodology is covered under Verification Engineer.)
- 📝👶 SystemVerilog TestBench
- 🔗 EDA Playground - Run simulations in the browser
- 🔗 cocotb - Python-based testbenches for VHDL and Verilog
- 🔗 WaveDrom
- 🔗 DigitalJS
- 🔗 Monosketch
- 📝 Debugging with Speed and Precision: Mastering the Art of FPGA Debugging
- 📝 Vivado Design Suite User Guide: Programming and Debugging (UG908) - ILA and VIO debug cores
- 🔗 Verible - SystemVerilog parser, linter and formatter
Priority: Required
What is inside an FPGA: look-up tables (LUTs), flip-flops, carry chains, block RAM, DSP slices, clocking resources (PLL/MMCM), I/O standards and routing. Knowing the architecture explains why some code maps well to hardware and some does not.
- 📝👶 Field-programmable gate array - Wikipedia
- 📝 7 Series FPGAs Configurable Logic Block User Guide (UG474)
- 📝 7 Series FPGAs Memory Resources User Guide (UG473)
- 📝 7 Series FPGAs Clocking Resources User Guide (UG472)
- 📝 7 Series DSP48E1 Slice User Guide (UG479)
Priority: Required
Understanding of specific FPGA toolchains like Xilinx Vivado, Intel Quartus, etc. Vendor tools have free editions for most small and mid-size devices; open-source tools are a great way to understand what each step of the flow does.
Simulation, synthesis and place-and-route (open source):
- 🔗👶💎 OSS CAD Suite - Ready-to-use binary builds of Yosys, nextpnr, Verilator, Icarus Verilog, SymbiYosys and more
- 🔗 Yosys Open SYnthesis Suite
- 📝 Yosys Documentation
- 🔗 nextpnr
- 🔗 Icarus Verilog - Verilog simulator
- 🔗 Verilator - Fast SystemVerilog simulator and linter
- 🔗 GHDL - an open-source simulator for the VHDL language
- 🔗 GTKWave - a fully featured GTK+ based wave viewer
- 🔗 openFPGALoader - Universal utility for programming FPGAs
- 🔗 apio - Open-source ecosystem for FPGA boards
- 🔗 F4PGA - Open-source FPGA toolchain project
Vendor and commercial tools:
- 🔗 AMD (Xilinx) Design Tools
- 🔗 Intel (Altera) Development Tools
- 🔗 Lattice FPGA Design Software
- 🔗 Gowin EDA
- 🔗 ModelSim HDL simulator
- 🔗 Cadence Design Tools
- 🔗 Synopsys Design Tools
Priority: Required
Understanding the overall process of design, from specification to synthesis and place-and-route, is helpful in order to interface effectively with the design team.
- 📘 A Hands-On Guide to Designing Embedded Systems - Adam Taylor, Dan Binnun, Saket Srivastava
- 📝 Understanding FPGA Programming and Design Flow
- 📝 ASIC Design Flow in VLSI Engineering Services – A Quick Guide
- 📝 Vivado Design Suite User Guide: Design Flows Overview (UG892)
Priority: Required
A design only works if signals arrive on time. Learn setup and hold times, clock frequency and slack, critical paths, and how to write timing constraints (SDC/XDC) and read timing reports. Proficiency in these is what makes a design run at the intended clock speed.
- 📝💎 Vivado Design Suite User Guide: Using Constraints (UG903)
- 📝 Vivado Design Analysis and Closure Techniques (UG906)
- 🔗 OpenSTA - Open-source static timing analyzer
Priority: Required
Signals that cross between unrelated clocks, and resets that are not handled properly, are among the most common causes of intermittent hardware bugs. Learn synchronizers, handshakes, asynchronous FIFOs and reset strategies.
- 📝💎 Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog - Clifford E. Cummings
- 📝💎 Simulation and Synthesis Techniques for Asynchronous FIFO Design - Clifford E. Cummings
- 📝 Asynchronous & Synchronous Reset Design Techniques - Part Deux - Clifford E. Cummings
- 📝 Clock Domain Crossing - ZipCPU
- 🔗 More papers on synthesis, resets and CDC - Sunburst Design
Priority: Required
Real designs talk to other chips and blocks. Start with simple serial protocols (UART, SPI), then learn on-chip bus standards (AXI, AXI-Stream, Wishbone), and later memory (DDR) and high-speed interfaces (Ethernet, PCIe). Both implementation and verification engineers need to be aware of requirements, architecture, and interconnect standards and interfaces.
- 📝👶 RS-232 (UART) Serial Interface - FPGA4fun
- 📝👶 SPI - FPGA4fun
- 📝 Building a Simple AXI-Lite Slave - ZipCPU
- 📝 Designing a Custom AXI Slave (Avnet PDF)
- 🔗 AMBA AXI Protocol Specification - Arm
- 🔗 Wishbone B3 Specification
- 🔗 LiteDRAM - Small footprint and configurable DRAM core
- 🔗 Verilog Ethernet (Alex Forencich)
- 🔗 Verilog PCI Express Components (Alex Forencich)
Priority: Recommended
Familiarity with relevant industry standards can be important, especially in fields like telecommunications or automotive.
- 🔗 IEEE 1800 - SystemVerilog (free via IEEE Get Program)
- 🔗 The RISC-V Instruction Set Specifications
- 🔗 Accellera Standards (UVM, IP-XACT and more)
As an FPGA (Field Programmable Gate Array) implementation engineer, there are several important topics to be well-versed in:
Priority: Required
Understanding of various FPGA design techniques and best practices is important.
FPGA design methodologies encompass a broad range of techniques and strategies used in the process of designing and implementing digital logic on FPGA devices. Here are some key methods:
Register Transfer Level (RTL) design is a method where the digital system is described at a high level in terms of data flow between registers and the logical operations performed on the data. This allows the designer to focus on the logic functionality and data flow, rather than the specifics of how each gate is connected.
HLS is a design methodology where the digital system is described in a high-level programming language such as C or C++, and then automatically converted into RTL code by an HLS tool. This approach can be faster and easier than writing RTL code directly, especially for complex algorithms. It is an advanced topic; learn RTL first.
- 📘 High-Level Synthesis Made Easy: Synthesizing Behavioral Descriptions directly into Hardware Circuits
- 📘 High-Level Synthesis Blue Book - Michael Fingeroff
- 🔗 Vitis HLS — Vitis™ Tutorials
IP (Intellectual Property) cores are pre-designed circuit blocks that can be reused in multiple designs. Using IP cores can significantly speed up the design process and improve the reliability of the design, since the IP cores have been pre-verified.
- 📝 Basics of core-based FPGA design
- 📝 IP Cores For FPGA Designs
- 📝 So you want to Design a FPGA IP Core!
In many FPGA applications, a portion of the system functionality is implemented in software running on an embedded processor, while other portions are implemented in custom hardware on the FPGA. Hardware-software co-design involves designing the hardware and software components together to achieve the best overall system performance.
This design methodology prioritizes meeting timing constraints. This may involve strategies such as pipelining to increase clock speed, carefully partitioning the design to reduce routing congestion, or using timing constraints files to guide the place-and-route process.
This involves making the most efficient use of FPGA resources such as logic blocks, DSP blocks, and memory blocks. It might involve strategies such as sharing resources between multiple functions, or optimizing the logic to reduce the number of logic blocks used.
These methodologies are not mutually exclusive and can often be used together in the same design. The appropriate methodology to use depends on the specific design goals and constraints.
Priority: Recommended
Many modern FPGAs combine programmable logic with hard processor cores (for example AMD Zynq), or run a processor you build in the fabric (soft cores such as MicroBlaze or RISC-V). Working at this boundary needs both hardware and embedded software knowledge: bus interfaces, device drivers, booting and Linux.
- 📘👶 The Zynq Book
- 🔗 PYNQ - Python productivity for AMD adaptive computing platforms
- 🔗 LiteX - Build your own FPGA-based SoC in Python
- 🔗 VexRiscv - FPGA-friendly RISC-V CPU
- 🔗 PicoRV32 - Size-optimized RISC-V CPU
Priority: Recommended
Depending on the application, an understanding of digital signal processing concepts can be very useful.
- 📘💎 The Scientist and Engineer's Guide to Digital Signal Processing - Steven W. Smith
- 🔗 controlpaths - Blogs in control and signal processing
- 🎞️ Digital Signal Processing (ECSE-4530) Lectures, Fall 2014 (YouTube Playlist)
- 📘 Real-Time Digital Signal Processing: Fundamentals, Implementations and Applications - Sen M. Kuo, Bob H. Lee, Wenshun Tian
- 📘 Schaum's Outline of Signals and Systems - Hwei P. Hsu
- 📘💎 Digital Signal Processing - John G. Proakis, Dimitris K. Manolakis
- 🎞️ Discrete Fourier Transform - Simple Step by Step
- 🎞️ The Fast Fourier Transform (FFT): Most Ingenious Algorithm Ever?
- 🎞️ The FFT Algorithm - Simple Step by Step
Priority: Optional
Techniques to optimize the power consumption and manage heat dissipation.
Priority: Optional
When a design moves from a development board to custom hardware, you need to understand FPGA configuration and boot, power supplies and sequencing, pin assignment, and signal integrity for high-speed signals.
- 📝 7 Series FPGAs Configuration User Guide (UG470)
- 📝 UltraScale Architecture PCB Design User Guide (UG583)
Priority: Optional (advanced)
FPGA vendors do not publish the format of the bitstream (the file that configures the chip). Open-source projects document it by generating many small designs with vendor tools and analyzing how each change affects the bitstream (fuzzing), then store the result in a database used by open synthesis and place-and-route tools. This is advanced work that needs solid knowledge of FPGA architecture, the toolchain and scripting (Python, Tcl) first. The usual learning path is: master FPGA Architecture and the FPGA Toolchain, run the open-source flow on a supported board, then read the documentation of a project such as Project X-Ray (Xilinx 7 Series) and reproduce its fuzzers. Check the license and terms of use of the vendor tools you analyze.
- 📝💎 Project X-Ray - Documenting the Xilinx 7-series bitstream format
- 🔗 Project X-Ray - Source code and fuzzers
- 🔗 Project X-Ray Database - Bitstream documentation for Xilinx 7 Series
- 🔗 nextpnr-xilinx - Place and route for Xilinx 7 Series using Project X-Ray
- 🔗 openXC7 - Open-source toolchain for Xilinx 7 Series
- 🔗 Project IceStorm - Documenting the Lattice iCE40 bitstream
- 🔗 Project Trellis - Documenting the Lattice ECP5 bitstream
- 🔗 Apicula - Open-source tools for Gowin FPGAs
- 🔗 Mistral - Documenting the Intel Cyclone V bitstream
- 🔗 F4PGA - Open-source FPGA toolchain project
- 🔗 RapidWright - Framework for building custom tools on top of AMD Vivado
Priority: Recommended
Including proficiency in languages such as C/C++, Python, and knowing how to work with software drivers for hardware interfaces.
Priority: Optional
Understanding of embedded system design, including both hardware and software aspects.
Priority: Optional
FPGAs are used in networking, video and imaging, software-defined radio, motor control, finance, hardware security, and machine-learning acceleration. Pick a domain that interests you and build a project in it.
- 🔗 hls4ml - Machine learning inference on FPGAs
- 🎞️ Coursera - Hardware Security
- 🔗 Verilog Ethernet (Alex Forencich)
The other side of the coin is the verification engineer, who plays a crucial role in the development of hardware and software systems by ensuring the design meets the specified requirements. Verification is a large part of both FPGA and ASIC projects, and in ASIC work it usually takes more effort than design itself. Here are several important subjects and topics that a Verification Engineer should know:
Priority: Required
These include SystemVerilog, which is commonly used for hardware verification, and others like Property Specification Language (PSL).
- 📝 SystemVerilog Tutorial
- 📝 SystemVerilog Tutorial - ChipVerify
- 📝 SystemVerilog.io
- 📝 Sv-lang
- 📝 VLSI Verify
- 📝 Property Specification Language (PSL) - Wikipedia
Priority: Required
Verification engineers must know how to develop testbenches to simulate and verify the functionality and performance of a design, including self-checking testbenches, reference models and scoreboards.
- 🔗 cocotb - Python-based testbenches for VHDL and Verilog
- 🔗 VUnit - Unit testing framework for VHDL/SystemVerilog
- 🔗 OSVVM - Open Source VHDL Verification Methodology
- 🔗 UVVM - Universal VHDL Verification Methodology
- 🔗💎 Verification Academy - Courses, cookbooks and forums
- 📝 The Python for Verification Series
- 🔗 cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Priority: Required
Constrained-random stimulus finds corner cases that hand-written tests miss. Assertions and functional coverage are key for ensuring the design behaves as expected under all conditions, and for making sure all important scenarios are tested.
- 📝 SystemVerilog Randomization - ChipVerify
- 📝 SystemVerilog Assertions - ChipVerify
- 📝 SystemVerilog Functional Coverage - ChipVerify
- 🔗 Coverage Cookbook - Verification Academy
- 🔗 cocotb-coverage - Functional coverage and constrained randomization for cocotb
- 📘💎 SystemVerilog for Verification - Chris Spear , Greg Tumbush
Priority: Recommended
This is an industry-standard methodology for verification of hardware designs, and is expected in most ASIC verification jobs.
- 🔗 UVM (Standard Universal Verification Methodology)
- 📝 UVM 1.2 User Guide
- 📝👶 UVM Guide for Beginners
- 📝👶 Easier UVM - Doulos
- 🔗 UVM Cookbook - Verification Academy
- 🔗 pyuvm - Python implementation of UVM on top of cocotb
- 📘 The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology - Ray Salemi
Priority: Recommended
Including equivalence checking and model checking.
- 📝👶💎 Verilog, Formal Verification and Verilator Beginner's Tutorial
- 📝 SymbiYosys - Open-source formal verification flow
- 📝 11 Myths About Formal Verification
- 📝 Verilator Direct Programming Interface
ASIC (Application-Specific Integrated Circuit) engineers take RTL through synthesis, floorplanning, placement, clock tree synthesis, routing and sign-off to produce the final chip layout (GDSII). Since a chip cannot be patched after fabrication, verification, timing sign-off and physical checks are even more critical than in FPGA design. Open-source tools and open process design kits (PDKs) now let anyone learn this flow for free. The front-end work (RTL, verification, synthesis, DFT) builds directly on the Common Skills and Verification sections above; the back-end work is physical design.
Priority: Required
The complete path from RTL to a manufacturable layout, using free tools. Tiny Tapeout and the Zero to ASIC Course are the easiest way to run this flow end to end.
- 🔗👶💎 Zero to ASIC Course
- 🔗👶💎 Tiny Tapeout: from idea to chip design in minutes!
- 📝💎 LibreLane - Open-source ASIC implementation flow
- 🔗 OpenROAD Project
- 📝 OpenROAD Documentation
- 🔗 OpenROAD-flow-scripts
- 🔗 Yosys Open SYnthesis Suite
Priority: Recommended
Testability features are added to the hardware design to make it easier to test and debug manufactured chips. This includes scan chains, automatic test pattern generation (ATPG) and built-in self-test (BIST). Unlike FPGAs, every manufactured ASIC must be tested, so DFT is a core ASIC skill.
Priority: Recommended
Techniques such as clock gating, power gating and multiple voltage domains, described with the Unified Power Format (UPF). Power is usually a key constraint in chip projects. Learn the basics from the commercial tool documentation and training of Cadence and Synopsys.
Priority: Recommended
A PDK describes a foundry's manufacturing process (cell libraries, design rules, device models). Open PDKs are what make open-source chip design possible.
- 🔗 SkyWater SKY130 PDK
- 📝 SkyWater SKY130 PDK Documentation
- 🔗 GlobalFoundries GF180MCU PDK
- 🔗 IHP Open PDK (SG13G2 SiGe BiCMOS)
Priority: Recommended
Viewing and editing layouts, checking design rules (DRC) and layout-versus-schematic (LVS), and verifying timing before tape-out.
- 🔗 KLayout - Layout viewer and editor
- 🔗 Magic VLSI Layout Tool
- 🔗 Netgen - LVS and netlist comparison tool
- 🔗 OpenSTA - Open-source static timing analyzer
Priority: Recommended
How transistors form gates and how gate-level behavior, delay and power follow from the circuit level.
- 📘💎 CMOS VLSI Design: A Circuits and Systems Perspective - Neil Weste, David Harris
- 🎞️ Coursera - VLSI CAD Part I: Logic
- 🎞️ YouTube Playlist - CMOS Digital VLSI Design
Priority: Optional
Even digital ASICs contain analog blocks (PLLs, ADCs, I/O). Digital engineers benefit from knowing circuit simulation and schematic capture to understand what these blocks need from the digital side.
Priority: Optional
Large ASICs are usually prototyped on FPGAs before fabrication. Tape-out is the hand-off of the final layout to the foundry; low-cost shuttle services let students and hobbyists get real chips made.
- 🔗 Tiny Tapeout: from idea to chip design in minutes!
- 🔗 wafer.space - Open-source silicon shuttle runs
Hardware design is easier with other people to ask. Search before asking, share your code and the exact error message, and be specific about what you tried:
- 🔗 r/FPGA
- 🔗 r/chipdesign
- 🔗 EEVblog Forum - FPGA
- 🔗 Electronics Stack Exchange - fpga tag
- 🔗 Verification Academy Forums
- 🔗 Awesome HDL - Curated list of hardware design resources
Typical entry-level roles are RTL/FPGA design engineer, design verification (DV) engineer, and physical design engineer. A public portfolio (simulated and hardware-tested projects on GitHub, ideally with testbenches and a README explaining the design) is the best way to show your skills, and interview preparation usually focuses on digital logic, FSMs, timing and clock domain crossing, and HDL coding questions:
If you are an experienced FPGA or ASIC engineer, or a learner who found something that really helped, your input is welcome. In particular:
- Which topics are missing or misplaced in this roadmap?
- What are the best resources you know for each topic?
Please open an issue or make a pull request with your suggestions, and read the contribution guidelines before adding resources.
This roadmap started as a discussion on Reddit to gather information, categorize it under different topics, and decide how important each one is. Special thanks to u/No_Delivery_1049, whose comment served as the base of this roadmap, and to everyone who has contributed since.