RegFile.jsim

.subckt regfile clk werf ra2sel ra[4:0] rb[4:0] rc[4:0] rc_wb[4:0]
+ wdata[31:0] radata[31:0] rbdata[31:0]

    Xtrue_vdd vdd constant1
    Xregfile
    + vdd 0 0 ra[4:0] adata[31:0] // A read port
    + vdd 0 0 ra2mux[4:0] bdata[31:0] // B read port
    + 0 clk werf wa[4:0] wdata[31:0] // write port
    + $memory width=32 nlocations=31
    Xtrue 1 constant1 //tmp
    Xregfile_mux2 b_ra2sel#5 rb[4:0] rc[4:0] ra2mux[4:0] mux2

    // determine if a address is 0b11111 for R31
    Xreg_nand3_1 ra[4:2] tmp1 nand3
    Xreg_nand2_1 ra[1:0] tmp2 nand2
    Xreg_nor2_1 tmp1 tmp2 a31sel nor2

    // determine if b port address is R31
    Xreg_nand3_2 ra2mux[4:2] tmp3 nand3
    Xreg_nand2_2 ra2mux[1:0] tmp4 nand2
    Xreg_nor2_2 tmp3 tmp4 b31sel nor2

    // mux to determine what goes to read ports
    Xregfile_mux2_2 b_a31sel#32 adata[31:0] 0#32 radata[31:0] mux2
    Xregfile_mux2_3 b_b31sel#32 bdata[31:0] 0#32 rbdata[31:0] mux2

    // write to rc
    Xrename_wa rc_wb[4:0] wa[4:0] knex

    // buffer high load inputs
    Xreg_buff_0 a31sel b_a31sel buffer_8
    Xreg_buff_1 b31sel b_b31sel buffer_8
    Xreg_buff_2 ra2sel b_ra2sel buffer_2
.ends